SPOL3=LOW, SPOL1=LOW, SPOL0=LOW, CPOL=LOW, ENABLE=DISABLED, SPOL2=LOW, LOOP=DISABLED, LSBF=STANDARD, CPHA=CHANGE, MASTER=SLAVE_MODE
SPI Configuration register
| ENABLE | SPI enable. 0 (DISABLED): Disabled. The SPI is disabled and the internal state machine and counters are reset. 1 (ENABLED): Enabled. The SPI is enabled for operation. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| MASTER | Master mode select. 0 (SLAVE_MODE): Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 1 (MASTER_MODE): Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. |
| LSBF | LSB First mode enable. 0 (STANDARD): Standard. Data is transmitted and received in standard MSB first order. 1 (REVERSE): Reverse. Data is transmitted and received in reverse order (LSB first). |
| CPHA | Clock Phase select. 0 (CHANGE): Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. 1 (CAPTURE): Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. |
| CPOL | Clock Polarity select. 0 (LOW): Low. The rest state of the clock (between transfers) is low. 1 (HIGH): High. The rest state of the clock (between transfers) is high. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| LOOP | Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. 0 (DISABLED): Disabled. 1 (ENABLED): Enabled. |
| SPOL0 | SSEL0 Polarity select. 0 (LOW): Low. The SSEL0 pin is active low. The value in the SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL0 is not inverted relative to the pins. 1 (HIGH): High. The SSEL0 pin is active high. The value in the SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL0 is inverted relative to the pins. |
| SPOL1 | SSEL1 Polarity select. 0 (LOW): Low. The SSEL1 pin is active low. The value in the SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL1 is not inverted relative to the pins. 1 (HIGH): High. The SSEL1 pin is active high. The value in the SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL1 is inverted relative to the pins. |
| SPOL2 | SSEL2 Polarity select. 0 (LOW): Low. The SSEL2 pin is active low. The value in the SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL2 is not inverted relative to the pins. 1 (HIGH): High. The SSEL2 pin is active high. The value in the SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL2 is inverted relative to the pins. |
| SPOL3 | SSEL3 Polarity select. 0 (LOW): Low. The SSEL3 pin is active low. The value in the SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL3 is not inverted relative to the pins. 1 (HIGH): High. The SSEL3 pin is active high. The value in the SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL3 is inverted relative to the pins. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |